Radiation-Resilient Volatile Memory for Satellite Systems: A Review of Fault-Aware Design Techniques for SRAM and DRAM

Abstract

The escalating complexity of modern satellite missions ranging from high-resolution Earth observation to deep-space exploration has driven a transition from specialized radiation-hardened-by-process components toward high-density Commercial-Off-The-Shelf (COTS) volatile memories. While Static Random-Access Memory (SRAM) and Dynamic Random-Access Memory (DRAM) offer the high-speed data processing required for these applications, they remain critically susceptible to the harsh extra-terrestrial radiation environment. This environment is characterized by Total Ionizing Dose (TID) effects and Single Event Effects (SEE), which induce "soft errors" that can compromise mission integrity or lead to catastrophic system failure.

This review paper provides a comprehensive analysis of state-of-the-art Fault-Aware Design Techniques and Radiation Hardening by Design (RHBD) strategies specifically engineered for satellite-based volatile memory. As CMOS technology scales into the deep-submicron and nanoscale regimes (below 28nm), the critical charge of memory nodes decreases significantly, facilitating not only Single Event Upsets (SEU) but also increasingly prevalent Single Event Multiple-Node Upsets (SEMNU). We perform a detailed evaluation of advanced SRAM cell architectures, including the RHRSE-20T, EWS-16T, and DICE cells, focusing on their ability to achieve self-recovery through redundant feedback loops and multi-node interlocks.

Furthermore, the paper investigates mitigation strategies for DRAM, where radiation-induced leakage in storage capacitors necessitates adaptive refresh rates and hardened sense amplifiers. Beyond the circuit level, we examine system-level reliability enhancements such as Triple Modular Redundancy (TMR), Error Correction Codes (ECC), and proactive memory scrubbing to prevent the accumulation of bit-flips. By comparing key performance metrics including Read Static Noise Margin (RSNM), silicon area overhead, and power consumption this review highlights the critical trade-offs inherent in designing for space. We conclude by identifying future trends in hybrid memory architectures, suggesting that a multi-layered approach combining ultra-hardened bit-cells with intelligent software-level fault mapping is the most viable path forward for the "New Space" era of resilient satellite computing.